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Nibble Mode DRAM
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1 dictionary results for: Nibble Mode DRAM
Free On-line Dictionary of Computing - Cite This Source - Share This

Nibble Mode DRAM storage
A standard DRAM where four successive bits can be clocked out of the single data line by successive pulses on the CAS\ line while RAS\ is active. A column address is only required for the first bit.
This mode is now unfashionable but can be found on some older 64 kilobit and 256 kilobit chips.
(1997-12-03)

The Free On-line Dictionary of Computing, © 1993-2007 Denis Howe
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