level-sensitive scan design

Computing Dictionary

level-sensitive scan design definition


(circuit design) (LSSD) A kind of scan design which uses separate system and scan clocks to distinguish between normal and test mode. Latches are used in pairs, each has a normal data input, data output and clock for system operation. For test operation, the two latches form a master/slave pair with one scan input, one scan output and non-overlapping scan clocks A and B which are held low during system operation but cause the scan data to be latched when pulsed high during scan.
____ | | Sin ----|S | A ------|> | | Q|---+--------------- Q1 D1 -----|D | | CLK1 ---|> | | |____| | ____ | | | +---|S | B -------------------|> | | Q|------ Q2 / SOut D2 ------------------|D | CLK2 ----------------|> | |____|
In a single latch LSSD configuration, the second latch is used only for scan operation. Allowing it to be use as a second system latch reduces the silicon overhead.
(1995-02-15)

The Free On-line Dictionary of Computing, © Denis Howe 2010 http://foldoc.org
Cite This Source
Explore Dictionary.com
Previous Definition: level-off
Next Definition: level-significance
More from Thesaurus.com
Synonyms and Antonyms for level-sensitive scan design
More from Reference.com
Search for articles containing level-sensitive scan design
Dictionary.com Word FAQs

Dictionary.com presents 366 FAQs, incorporating some of the frequently asked questions from the past with newer queries.

Copyright © 2014 Dictionary.com, LLC. All rights reserved.
  • Please Login or Sign Up to use the Recent Searches feature